Semiconductor device and process for producing semiconductor device

ABSTRACT

A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-006752, filed on Jan. 17, 2012, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor device and a process for producing semiconductor device.

BACKGROUND

A substrate (wafer) with semiconductor elements and a multiple-wiring-layer structure formed thereon is scribed and divided into respective product regions (chips). Around each of the product regions, scribe regions to be scribed are secured. Slightly inside the outer peripheral line of each product region, a moisture-resistant ring for preventing the intrusion of water into the product region from outside is formed. See JP 2010-238877 A and JP 2009-21528 A.

If the semiconductor wafer is cut in the scribe regions, cracks may occur from cut portions into the product regions as the case may be. If the cracks should reach product regions, the reliability of the products declines.

SUMMARY

According to one aspect of the present invention, a semiconductor device includes: a substrate in which a product region and scribe regions surrounding the product region are defined; a 1st insulation film formed above the substrate; a 1st metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the 1st metal film; a 1st groove disposed more inside than the 1st metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the 1st metal film; and a 2nd groove disposed more outside than the 1st metal film in such a manner as to surround the 1st metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the 1st metal film.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a plan view of a semiconductor wafer used for the semiconductor device of Example 1, and FIG. 1B is an expanded plan view illustrating product regions and scribe regions.

FIGS. 2 to 14 are sectional views illustrating the semiconductor device of Example 1 in a process of being produced.

FIGS. 15 to 19 are sectional views illustrating the semiconductor device of a comparative example in a process of being produced.

FIG. 20 is a sectional view illustrating the semiconductor device of Example 2 in a process of being produced.

FIG. 21 is a sectional view illustrating the semiconductor device of Modified Example 1 of Example 2 in a process of being produced.

FIG. 22 is a sectional view illustrating the semiconductor device of Modified Example 2 of Example 2 in a process of being produced.

FIG. 23 is a plan view illustrating the semiconductor device of Example 2.

DESCRIPTION OF EMBODIMENTS Example 1

FIG. 1A is a plan view illustrating a semiconductor wafer (30) used for the semiconductor device of Example 1. As the semiconductor wafer (30), for example, a silicon wafer is used. On the surface of the semiconductor wafer (30), a plurality of product regions (chip regions) (31) disposed in a matrix are defined. Between the respective product regions (31), scribe regions (32) are secured. The planar form of the scribe regions is a square lattice.

FIG. 1B is a plan view illustrating some product regions (31) and some scribe regions (32). In the product regions (31), moisture-resistant rings (37) are formed, and in the scribe regions (32), crack protection rings (34) are formed. Each crack protection ring (34) is disposed for each product region (31) and surrounds the corresponding product region (31). The planar form of each product region (31) is a rectangle or square, and the crack protection ring (34) includes the straight line portions extending in parallel to the respective sides of each product region (31). Each moisture-resistant ring (37) is disposed slightly inside the outer peripheral line of each product region (31). After completion of wafer process, the semiconductor wafer (30) (FIG. 1A) is scribed along the center scribe lines (33) positioned at the centers in the width directions of the respective scribe regions (32).

In reference to FIGS. 2 to 14, the process for producing the semiconductor device of Example 1 is explained. FIGS. 2 to 14 correspond to the sectional views at the position of the one-dot-dash line 2-2 of FIG. 1B.

In the central portion of FIG. 2, a scribe region (32) is disposed, and product regions (31) are disposed on both sides of the scribe region. In the surface layer portion of the product regions (31) and the scribe regions (32) of the semiconductor wafer (30), element separation insulating films (40) are formed. The element separation insulating films (40) are formed by the shallow trench isolation (STI) method or LOCOS (LOCal Oxidation of Silicon) method.

The element separation insulating films (40) in each scribe region (32) have a planar form to surround the corresponding product regions (31), and the width thereof is, for example, 1 μm to 2 μm. The element separation insulating films (40) in the product regions (31) and the scribe regions (32) have a depth of, for example, 320 nm. In the active region surrounded by the element separation insulating films (40) in each product region (31), a MOS transistor (41) is formed.

On the semiconductor wafer (30), an insulation film (42) as a 1st via layer is formed to cover the MOS transistors (41). An example of the method for forming the insulation film (42) is explained below. At first, plasma-enhanced chemical vapor deposition (PE-CVD) is used to form an approx. 20 nm-thick silicon oxide film, and on the silicon oxide film, an 80 nm-thick silicon nitride film is formed. Further on the silicon nitride film, an approx. 1300 nm-thick borophosphosilicate glass (BPSG) film is formed, and annealing is performed at 650° C. for 120 seconds. An approx. 1000 nm-thick silicon oxide film may also be formed by CVD by using tetraethoxysilane (TEOS) and O₂ or O₃ as an alternative to the BPSG film. In this description, the silicon oxide film formed by CVD by using TEOS and O₂ or O₃ is called a TEOS film.

After forming the BPSG film, the surface is flattened by chemical mechanical polishing (CMP). On the flattened surface, an approx. 100 nm-thick silicon oxide film is formed by PE-CVD. The insulation film (42) has a laminate structure in which a silicon oxide film, a silicon nitride film, BPSG film and a silicon oxide film are laminated in this order. The thickness of the insulation film (42) is, for example, 450 nm.

Contact holes (42A) and grooves (42B) and (42C) are formed in the insulation film (42). Each contact hole (42A) partially exposes the source or drain of the corresponding MOS transistor (41). Each groove (42B) is formed in each product region (31), and has a planar form corresponding to that of the moisture-resistant ring (37) illustrated in FIG. 1B. Grooves (42C) partially overlap the corresponding element separation insulating films (40) in the corresponding scribe region (32), and have a planar form corresponding to that of the crack protection ring (34) illustrated in FIG. 1B. The edge of each groove (42C) on the inner peripheral side is positioned more on the product region (31) side than the edge of the corresponding element separation insulating film (40) on the inner peripheral side. The width of each groove (42C) disposed at the position of the corresponding crack protection ring (34) and the width of each groove (42B) disposed at the position of the moisture-resistant ring (37) are, for example, 0.1 μm.

Each contact hole (42A) formed in the insulation film (42) is filled with a contact plug (43A), and each groove (42B) is filled with a metal film (43B), while each groove (42C) is filled with a metal film (43C). The contact plugs (43A) and the metal films (43B) and (43C), each, contain a barrier metal film and a tungsten member. The barrier metal film has, for example, a two-layer structure including a 10 nm-thick Ti film and a 10 nm-thick TiN film.

On the insulation film (42), an insulation film (44) of a 1st wiring layer is formed. The insulation film (44) has, for example, a three-layer structure including a 30 nm-thick silicon carbide (SiC) film, a 130 nm-thick silicon oxide carbide (SiOC) film and a 100 nm-thick TEOS film. In the insulation film (44), copper wirings (45) are formed. In order to form the wirings (45), a single damascene process is applied. At the positions of each moisture-resistant ring (37) and each crack protection ring (34), metal films (45B) and (45C) are formed respectively. The widths of the metal films (45B) and (45C) are approx. 4 μm.

On the insulation film (44) and the wirings (45), 2nd to 7th wiring layers (46) are formed. In order to form these wiring layers (46), a dual damascene process is applied.

Each of the insulation films of the 2nd to 5th wiring layers (46) has, for example, a 3-layer structure including a 60 nm-thick SiC film, a 450 nm-thick SiOC film and a 100 nm-thick TEOS film. Each of the insulation films of the 6th and 7th wiring layers (46) has, for example, a 3-layer structure including a 70 nm-thick SiC film, a 920 nm-thick SiOC film and a 30 nm-thick TEOS film.

In each of the insulation films of the respective wiring layers (46), wirings and contact plugs formed of copper or copper alloy are disposed. In each of the 2nd to 5th wiring layers, the depth from the top surface of the insulation film to the bottom surface of the wiring is approx. 275 nm. In each of the 6th and 7th wiring layers, the depth from the top surface of the insulation film to the bottom surface of the wiring is approx. 500 nm.

In each of the 2nd to 7th wiring layers (46), in the regions corresponding to each moisture-resistant ring (37) and each crack protection ring (34), metal films (47) and (48) are respectively disposed. The metal films (47) and (48) are formed of copper or copper alloy, and are formed simultaneously with the wirings and contact plugs in the corresponding wiring layer (46). The respective metal films (47) and (48) have planar forms corresponding to those of the moisture-resistant rings (37) and the crack protection rings (34) illustrated in FIG. 1B.

In each of the 2nd to 5th wiring layers (46), the widths of the metal films (47) and (48) in the portions having the same depths as those of the contact plugs are approx. 0.09 μm. In each of the 6th and 7th wiring layers (46), the widths of the metal films (47) and (48) in the portions having the same depths as those of the contact plugs are approx. 0.28 μm. In each of the 2nd to 7th wiring layers (46), the widths of the metal films (47) and (48) in the portions having the same depths as those of the wirings are approx. 4 μm.

Each metal film (47) contacts the corresponding metal film (47) of the wiring layer (46) present immediately below it and contacts the corresponding metal film (47) of the wiring layer (46) present immediately above it. Each metal film (48) also contacts the corresponding metal film (48) of the wiring layer (46) present immediately below it and contacts the corresponding metal film (48) of the wiring layer (46) present immediately above it. The respective metal films (47) and (48) of the 2nd wiring layer (46) contact the respectively corresponding metal films (45B) and (45C) in the 1st wiring layer (44).

On the 7th wiring layer (46), an 8th wiring layer (51) and a 9th wiring layer (52) are formed. Also for forming the 8th and 9th wiring layers (51) and (52), a dual damascene process is applied. Each of the insulation films of the 8th and 9th wiring layers (51) and (52) has, for example, a 2-layer structure including a 70 nm-thick SiC film and a 1500 nm-thick SiO₂ film. In each of the 8th and 9th wiring layers (51) and (52), the depth from the top surface of the insulation film to the bottom surface of the wiring is approx. 800 nm.

In the regions corresponding to each moisture-resistant ring (37) and each crack protection ring (34) in the insulation film of the 8th wiring layer (51), metal films (53) and (54) are respectively disposed. In the regions corresponding to each moisture-resistant ring (37) and each crack protection ring (34) in the insulation film of the 9th wiring layer (52), metal films (55) and (56) are respectively disposed. Of the metal films (53) to (56), the widths of the metal films in the portions having the same depths as those of the contact plugs are approx. 0.42 μm, and the widths of the metal films in the portions having the same depths as those of the wirings are approx. 4 μm.

The metal films (53) and (54) in the 8th wiring layer (51) respectively contact the corresponding metal films (47) and (48) in the 7th wiring layer (46). The metal films (55) and (56) in the 9th wiring layer (52) respectively contact the corresponding metal films (53) and (54) in the 8th wiring layer (51).

FIGS. 3 to 14 illustrate structures by omitting the structure of the 7th wiring layer (46) and below. As illustrated in FIG. 3, on the 9th wiring layer (52), an insulation film (60) is formed. The insulation film (60) is formed, for example, of two layers including a 70 nm-thick SiC film (60A) and a 1200 nm-thick SiO₂ film (60B). After the SiO₂ film (60B) is deposited, the surface portion is polished by approx. 300 to approx. 400 nm by means of CMP. The thickness of the flattened insulation film (60) is approx. 1 μm.

In the insulation film (60), via holes (61) and grooves (62) are formed. Each via hole (61) exposes the surface of the corresponding wiring of the lower layer. Each groove (62) exposes the surface of the corresponding metal film (55) of the lower layer forming a portion of the corresponding moisture-resistant ring (37). The width of each groove (62) is, for example, 0.4 μm. Each via hole (61) is filled with a contact plug (63), and each groove (62) is filled with a metal film (64). Each contact plug (63) and each metal film (64) contain a barrier metal film and a tungsten film.

On the insulation film (60), electrode pads (65) and metal films (66) and (67) are formed, for example, by using aluminum. Meanwhile, metal films different in etching properties from the metal films (55) and (56) of the 9th wiring layer (52) may also be used as an alternative to Al. The electrode pads (65) and the metal films (66) and (67), each, have a thickness of, for example, 1100 nm. Each electrode pad (65) is connected with the corresponding contact plug (63) of the lower layer. Each metal film (66) forms a portion of the corresponding moisture-resistant ring (37). Each metal film (67) is disposed above the corresponding metal film (56) forming the corresponding crack protection ring (34), and has a planar form surrounding the corresponding product region (31).

A protection film (70) is formed on the insulation film (60), the electrode pads (65) and the metal films (66) and (67). The protection film (70) is formed, for example, of two layers including a 1400 nm-thick SiO₂ film (70A) and a 500 nm-thick SiN film (70B).

As illustrated in FIG. 4, a mask pattern (73) is formed on the protection film (70). The mask pattern (73) is formed, for example, of a photoresist. In the mask pattern (73), openings (73A) and (73B) are formed. Each opening (73A) is disposed above the corresponding electrode pad (65) and is included in the electrode pad (65) on a plan view. Each opening (73B) is disposed above the corresponding crack protection ring (34) and includes the metal film (67) on a plan view.

The edge of each opening (73B) on the inner peripheral side is positioned more on the product region (31) side than the edge of the corresponding metal film (67) on the inner peripheral side, and the edge of each opening (73B) on the outer peripheral side is positioned more outside than the edge of the corresponding metal film (67) on the outer peripheral side.

As illustrated in FIG. 5, the mask pattern (73) is used as an etching mask, to etch the protection film (70). The etching forms a pad opening portion (75) at the position of each opening (73A). At the bottom surface of the pad opening portion (75), the corresponding electrode pad (65) is exposed. In the region where each opening (73B) is formed, the corresponding metal film (67) is exposed. Even after exposing the electrode pads (65) and the metal films (67), etching is continued.

Each metal film (67) acts as an etching mask, to form a groove (77) on the inner peripheral side of the corresponding metal film (67), and to form a groove (78) on the outer peripheral side. Etching is performed till the depths of the grooves (77) and (78) become deeper than the top surface of the corresponding metal film (56) disposed in the insulation film (52). FIG. 5 illustrates a case where the grooves (77) and (78) reach the same depth as that of the bottom surface of the insulation film (52), i.e., reach the same depth as that of the bottom surface of the corresponding metal film (56). After the grooves (77) and (78) are formed, the mask pattern (73) is removed. Each metal film (67) acts as an etching mask, and consequently even after the grooves (77) and (78) are formed, each metal film (56) formed of Cu below the corresponding metal film (67) is not exposed. Because of this configuration, the production device used in these steps and in the subsequent steps (including the re-wiring step) can be prevented from being contaminated by Cu. With the steps performed so far, the wafer process is completed. Subsequently, the re-wiring step of wafer level chip size package (WLCSP) is performed.

As illustrated in FIG. 6, on the protection film (70), a lower resin film (80) is formed. For the lower resin film (80), for example, a polyimide is used. In the lower resin film (80), openings (80A) each containing a pad opening portion (75) are formed on a plan view. In the scribe regions (32), the lower resin film (80) is not formed.

As illustrated in FIG. 7, on the entire exposed surface, a seed film (81) is formed. The seed film (81) is formed, for example, of two layers including a Ti film and a Cu film. In order to form the seed film (81), for example, sputtering is applied. The bottom surfaces and the lateral surfaces of the grooves (77) and (78) are also covered with the seed film (81).

As illustrated in FIG. 8, a resist film (82) is formed on the seed film (81). In the resin film (82), openings (82A) corresponding to the wiring pattern to be formed are formed. The scribe regions (32) are covered with the resist film (82). With the seed film (81) as an electrode, the seed film (81) at the bottom surface of each opening (82A) is plated with copper. With this operation, copper wirings (85) are formed. After the wirings (85) are formed, the resist film (82) is removed. The seed film (81) that had been covered with the resist film (82) is exposed.

As illustrated in FIG. 9, the exposed seed film (81) (see FIG. 8) is removed by dry etching. Subsequently, an alkali chemical solution treatment is applied to perform a surface treatment. With this operation, the insulation among the plurality of wirings (85) can be secured. At the same time, with the chemical solution treatment, the metal films (67) disposed in the scribe regions (32) are also removed. Under the wirings (85), the seed film (81) remains.

As illustrated in FIG. 10, an upper resin layer (90) is formed on the lower resin film (80) and the wirings (85). For the upper resin film (90), for example, a polyimide is used. In the upper resin film (90), openings (90A) are formed. Each opening (90A) is disposed within the corresponding wiring (85) on a plan view, to partially expose the surface of the wiring (85). When the openings (90A) are formed, the upper resin film (90) on the scribe regions (32) is also removed.

On the entire exposed surface, a seed film (91) is formed. The seed film (91) is formed, for example, of 2 layers including a Ti film and a Cu film. For forming the Ti film and the Cu film, for example, sputtering is applied.

As illustrated in FIG. 11, on the seed film (91), a resist film (94) is formed. In the resist film (94), openings (94A) are formed. Each opening (94A) has a planar form almost overlying the corresponding opening (90A) formed in the upper resin film (90).

As illustrated in FIG. 12, with the seed film (91) as an electrode, the seed film (91) in each opening (94A) is plated with nickel (Ni). Further, the Ni plating layer is plated with SnAg. With this operation, a bump backing film (95) made of Ni and a bump (96) made of SnAg are formed in each opening (94A). After the bumps (96) are formed, the resist film (94) is removed.

As illustrated in FIG. 13, the bumps (96) are subjected to a reflow treatment. Then, the exposed seed film (91) is removed by etching. After etching the seed film (91), an alkali chemical solution is used to perform a surface treatment. With this operation, the insulation among the plurality of bumps (96) can be secured.

As illustrated in FIG. 14, the semiconductor wafer (30) is scribed at the center of each scribe region (32), to divide the respective product regions (31). If a crack (100) occurs during scribing, the crack (100) reaches the corresponding crack protection ring (34). Subsequently the crack (100) propagates along the interface between the crack protection ring (34) and the insulation films (51) and (52), etc. Finally, the crack (100) reaches the groove (77) formed more on the inner peripheral side than the crack protection ring (34), and is terminated at the groove (77). Accordingly, it can be prevented that the crack (100) propagates to the corresponding product region (31).

In reference to FIGS. 15 to 19, a semiconductor device production process as a comparative example is explained. In FIGS. 15 to 19, the respective components are given the same symbols as those of the corresponding components of the semiconductor device produced by the process of Example 1.

The structure illustrated in FIG. 15 corresponds to the structure illustrated in FIG. 5 for the process of Example 1. In Example 1, the edge of each opening (73B) on the outer peripheral side formed in the resist film (73) is disposed more outside than the corresponding metal film (67). In the comparative example illustrated in FIG. 15, the edge of each opening (73B) on the outer peripheral side overlies the corresponding metal film (67) on a plan view. Consequently, each groove (77) is formed only on the inner peripheral side of the corresponding metal film (67), and no groove is formed on the outer peripheral side.

The structure illustrated in FIG. 16 corresponds to the structure illustrated in FIG. 8 for the process of Example 1. In the comparative example, no groove is formed on the outer peripheral side of each metal film (67). Except the groove, the structure is identical to the structure of FIG. 8 for the process of Example 1.

The structure illustrated in FIG. 17 corresponds to the structure illustrated in FIG. 9 for the process of Example 1. If the metal films (67) are removed, the portion (70C) disposed on each metal film (67), of the protection film (70) remains like an edge of a roof. Immediately below the portion (70C) remaining like an edge of a roof, a cavity is formed.

The structure illustrated in FIG. 18 corresponds to the structure illustrated in FIG. 10 for the process of Example 1. In Example 1, the seed film (91) covers the entire area of the surface continuously, but in the comparative example, the continuity of the seed film (91) is suspended at the tip portion of each portion (70C) remaining like an edge of a roof.

The structure illustrated in FIG. 19 corresponds to the structure illustrated in FIG. 11 for the process of Example 1. Since the seed film (91) is not continuous, the seed film (91) cannot be used as an electrode for electrolytic plating. Accordingly, on the seed film (91) in each opening (94A), the bump backing film (95) and the bump (96) cannot be formed by electrolytic plating.

On the contrary, in Example 1, as illustrated in FIG. 9, even if each metal film (67) is removed, the portion like an edge of a roof does not remain. Therefore, the seed film (91) can be formed continuously on the surface of the substrate. With this operation, electrolytic plating can be applied to the formation of the bump backing film (95) and the bump (96).

Next, in reference to FIG. 5, the relative positional relationship among the metal film (56), the metal film (54), the metal film (67) and the opening (73B) is explained. The metal film (56) is disposed as the uppermost layer among the plurality of metal films forming each crack protection ring (34), and the metal film (54) is disposed as the 2nd layer from the top.

The width of the metal film (67) is denoted by Wa, and the widths of the metal films (56) and (54) are denoted by Wc. The interval between the edge of the metal film (56) on the inner peripheral side and the edge of the metal film (67) on the inner peripheral side is denoted by Wi. The maximum values of shifts of the metal films (56) and (54) from the design positions are denoted by Dm.

In this case, it is preferred that the design value of the interval Wi complies with the following inequality. Wi≧((0.25×Wc)² +Dm ²)^(1/2)

If the interval (Wi) is designed to comply with the inequality, it can be prevented that the metal films (56) and (54) formed of Cu are exposed when the groove (77) is formed. For example, if the width (Wa) is 3.2 μm and the width (Wc) is 2 μm, then it is preferred that the interval (Wi) is 0.6 μm or more. If the interval (Wi) is wide, the scribe region (32) becomes wide. Consequently it is not preferred that the interval (Wi) is wider than necessary. It is preferred that the interval (Wi) is 1.1 times or less of the right side of the formula.

The interval between the edge of the metal film (56) on the outer peripheral side and the edge of the metal film (67) on the outer peripheral side is denoted by Wo. It is preferred that the design value of the interval (Wo) complies with the following inequality like the interval (Wi). Wo≧((0.25×Wc)² +Dm ²)^(1/2)

The widths of the grooves (77) and (78) depend on the relative positional accuracy between the metal film (67) and the opening (73B). If a positional shift occurs causing the edge of the opening (73B) on the inner peripheral side overlies the metal film (67), the groove (77) cannot be formed. Considering the relative positional accuracy between the metal film (67) and the opening (73B), it is preferred that the widths of the grooves (77) and (78) are 1 μm or more. If the widths of the grooves (77) and (78) are made wider, the width of the scribe region (32) becomes wide. In order to inhibit the excessive increase of the width of the scribe region, it is preferred that the widths of the grooves (77) and (78) are 3 μm or less.

Example 2

FIG. 20 is a sectional view illustrating the semiconductor device of Example 2 in a process of being produced. The structure illustrated in FIG. 20 corresponds to the structure of the step illustrated in FIG. 5 of Example 1. In Example 1, one crack protection ring (34) is formed for each product region (31). In Example 2, outside the crack protection ring (34), a 2nd crack protection ring (110) is formed to surround the crack protection ring (34) on a plan view. The laminate structure of the crack protection ring (110) is the same as the laminate structure of the crack protection ring (34) of the inner peripheral side. That is, the crack protection ring (110) contains a metal film (114) in the wiring layer (52). Above the metal film (114), a metal film (113) acting as an etching mask is disposed.

On the inner peripheral side and on the outer peripheral side of the crack protection ring (110), grooves (111) and (112) are formed respectively. The grooves (111) and (112) are formed in the same step as that for forming the grooves (77) and (78) disposed on both sides of the crack protection ring (34) of the inner peripheral side.

If the crack protection ring (110) is formed further outside the crack protection ring (34), the performance for protecting from the propagation of cracks can be enhanced.

FIG. 21 is a sectional view illustrating the semiconductor device of Modified Example 1 of Example 2 in a process of being produced. In Modified Example 1, the grooves (78) and (111) illustrated in FIG. 20 are integrated to form one groove (115). If the grooves (78) and (111) are made to contact each other to form one groove (115), the width of the scribe region (32) can be narrowed.

FIG. 22 is a sectional view illustrating the semiconductor device of Modified Example 2 of Example 2 in a process of being produced. In Modified Example 2, the groove (112) of the outermost side illustrated in FIG. 21 is not formed. In Modified Example 1, when the grooves (77), (112) and (115) are formed, the region where the outside crack protection ring (110) is disposed is protected by the metal film (113). In Modified Example 2, the metal film (113) is not disposed, and the region where the outside crack protection ring (110) is disposed is protected by a resist film (73). Since the positioning margin for forming the groove (112) is not required to be secured, the scribe region (32) can be more narrowed.

FIG. 23 is a plan view illustrating a scribed semiconductor device produced by the process of Example 2. Outside the product region (31), the crack protection ring (34) of the inner peripheral side is disposed, and outside the crack protection ring (34), the crack protection ring (110) of the outer peripheral side is disposed. From an edge of the semiconductor device (105) obtained by dividing each product region (31), cracks (100) extend toward the inside.

Some cracks (100) cross the crack protection ring (110) of the outer peripheral side and reach the crack protection ring (34) of the inner peripheral side. The crack protection ring (34) of the inner peripheral side prevents the cracks (100) from reaching the product region (31). In this case, the crack protection ring (110) of the outer peripheral side is divided in the peripheral direction by the cracks (100).

As described above, after scribing, the crack protection rings (34) and (110) do not always continuously surround the periphery of the product region (31). Even in the case where the crack protection rings (34) and (110) are divided by cracks (100), the propagation of the cracks (100) into the product region (31) can be prevented.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A semiconductor device comprising: a substrate that includes a product region and a scribe region surrounding the product region; a 1st insulation film formed above the substrate; a 1st metal film, that is located in the scribe region of the substrate and surronds the product region of the substrate on a plan view parallel to the substrate, formed in the 1st insulation film; a 2nd insulation film formed on the 1st insulation film and the 1st metal film; a 1st groove, that surrounds the product region of the substrate and is surrounded by the 1st metal film on a plan view and that includes a 1st bottom located lower than a top surface of the 1st metal film, formed in the 2nd insulation film and at least part of the 1st insulation film; and a 2nd groove, that surrounds the 1st metal film on a plan view and that includes a 2nd bottom located lower than the top surface of the 1st metal film, formed in the 2nd insulation film and at least part of the 1st insulation film.
 2. The semiconductor device according to claim 1, further comprising: multiple wiring layers disposed between the substrate and the 1st insulation film; and conductive members, that surround the product region of the substrate on a plan view and that is connected to the substrate and the 1st metal film, disposed in the multiple wiring layers.
 3. The semiconductor device according to claim 1, further comprising a 3rd metal film, that is located in the scribe region of the substrate and surrounds the 2nd groove on a plan view parallel to the substrate, formed in the 1st insulation film.
 4. The semiconductor device according to claim 3, further comprising a 3rd groove, that surrounds the 3rd metal film on a plan view parallel to the substrate and that includes a 3rd bottom located lower than a top surface of a 3rd metal film, formed in the 2nd insulation film and at least part of the 1st insulation film.
 5. The semiconductor device according to claim 4, further comprising a 4th groove, that surrounds the 2nd groove and is surrounded by the 3rd metal film on a plan view and that includes a 4th bottom located lower than a top surface of the 3rd metal film, formed in the 2nd insulation film and at least part of the 1st insulation film.
 6. The semiconductor device according to claim 1, further comprising a 2nd metal film, that surrounds the 1st groove and is surrounded by the 2nd groove on a plan view and that includes a material different from a material of the 1st metal film, formed on the 1st insulation film. 